The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly it relates to a semiconductor device including a plurality of high power elements using a group III-V nitride semiconductor.
A group III-V nitride semiconductor is a compound semiconductor of a compound composed of aluminum (Al), boron (B), gallium (Ga) or indium (In) and nitride (N) represented by a general formula of BwAlxGayInzN (wherein w+x+y+z=1 and 0≦w, x, y, z≦1).
A group III-V nitride semiconductor has various advantages such as a large band gap, a high breakdown voltage derived from the large band gap, a high electron saturation velocity and high electron mobility, and a high electron concentration attained in forming a heterojunction, and therefore, various examinations and developments are now being made on application to a short-wavelength light emitting device, a high power high-frequency device, a high-frequency low-noise amplifier device, a high power switching device and the like.
Conventionally, such devices are developed as simplex devices for attaining performances that are realized by utilizing good material characteristics (physical properties) of a group III-V nitride semiconductor itself but cannot be realized by using other materials.
FIG. 11 is a cross-sectional view of a conventional group III-V nitride semiconductor device using a heterojunction (see, for example, Japanese Patent Publication No. 2996169 or 3409958). As shown in FIG. 11, the conventional group III-V nitride semiconductor device includes an operation layer 102 of gallium nitride (GaN) and a barrier layer 103 of aluminum gallium nitride (AlGaN) successively stacked on a semiconductor substrate 101 with a conducting property, and a heterojunction is formed on an interface between the operation layer 102 and the barrier layer 103 having different band gaps.
The barrier layer 103 is partitioned by an insulating isolation region 104 reaching an upper portion of the operation layer 102, a Schottky gate electrode 105 is formed on the partitioned barrier layer 103, and an ohmic source electrode 106 and an ohmic drain electrode 107 are formed on both sides of the gate electrode 105 along the gate length direction. Thus, the semiconductor device is operated as a heterojunction field effect transistor (hereinafter referred to as the HFET).
In the vicinity of the interface in the operation layer 102 of the heterojunction between the operation layer 102 and the barrier layer 103, electrons derived from a difference in spontaneous polarization and piezo-electric polarization between the operation layer 102 and the barrier layer 103, an n-type impurity doped in the barrier layer 103 and other uncontrollable defects caused in the operation layer 102 and the barrier layer 103 are accumulated in a high concentration so as to form a two-dimensional electron gas (2DEG), and the thus formed 2DEG works as a channel carrier of the field effect transistor.
The source electrode 106 is electrically connected to the semiconductor substrate 101 set to ground potential through a surface via interconnect 108, so as to reduce a parasitic component in a high-frequency or high-speed switching operation. Also, the semiconductor substrate 101 set to the ground potential functions also as a field plate (field releasing plate), and therefore, it exhibits an effect to release concentration of the electric field in a device active region, and particularly at an end of the gate electrode 105 closer to the drain electrode 107.
In the conventional group III-V nitride semiconductor device, however, current leakage is caused through the semiconductor substrate 101 in a high voltage operation, and therefore, it is difficult to electrically connecting or integrating a plurality of elements (HFETs) formed on one semiconductor substrate 101.